Basic Parameters
Layer Configuration
L1 (TOP)
Outer
L2 (GND)
Inner
L3 (SIG)
Inner
L4 (SIG)
Inner
L5 (PWR)
Inner
L6 (BOT)
Outer
Stack Up Visualization
1.600
Total Thickness (mm)
0.200
Dielectric L1-L2 (mm)
0.360
Core Thickness (mm)
~50Ω
Est. Impedance
Manufacturing Specs
| Parameter | Value |
|---|---|
| Min. Trace Width | 3.5 mil (0.09mm) |
| Min. Spacing | 3.5 mil (0.09mm) |
| Min. Via Drill | 0.2 mm |
| Aspect Ratio | 8:1 |
| Tolerance | ±10% |
| Lead Time | 5-7 Days |
6-Layer Design Tips
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Standard Configuration: Use Signal-GND-Signal-Signal-PWR-Signal for optimal EMI performance and signal integrity.
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Impedance Control: Keep consistent dielectric thickness between signal and reference planes for controlled impedance traces.
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Via Stitching: Use ground vias around high-speed signals to reduce crosstalk and EMI.
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Power Integrity: Add decoupling capacitors close to IC power pins for stable power delivery.
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Return Path: Ensure continuous ground plane under high-speed signal traces for proper return path.
Material Properties
| Property | FR4 Mid-Tg |
|---|---|
| Dielectric Constant (Dk) | 4.2 - 4.5 |
| Loss Tangent (Df) | 0.018 - 0.022 |
| Tg (Glass Transition) | 150°C |
| CTI | ≥ 175V |
| UL Rating | 94V-0 |